Reference Manual
audio - What does the FPGA do with unreferenced I/O pins? - Electrical Engineering Stack Exchange
Nios II Hardware Development Tutorial
AN 951: Intel® Stratix® 10 I/O Limited FPGA Design Guidelines
Pin settings | FPGA RGB Matrix | Adafruit Learning System
AN 174: Excalibur Solutions - Hello_world.c version 2.0 October 2001
DOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA Consider the design of a three-bit prime number detector completed in the MSOE
Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver Application Note
How to create a simple ColdFire and Altera FPGA IOC (Draft)
Verilog Basic | suda-morris's Personal Blog | Geek makes life better.
http://www.amy-studio.com/
Reserve_all_unused_pins | Altera Quartus II Settings File User Manual | Page 709 / 1344
CS-343 Assignment 3
Unused Pins Tab (Device & Pin Options Dialog Box)
How to configure Quartus II. Step by step guide | Details | Hackaday.io
Quartus Schematic tutorila
Implementing the MC8051 IP Core On A Cyclone Nios Board
在Quartus II中通过修改.qsf文件或TCL文件进行对器件和引脚的配置_Li-ion的博客-CSDN博客_qsf文件
DSP Dev Kit Cyclone II Edition User Guide Datasheet by Intel | Digi-Key Electronics
CS-343 Assignment 3
MAX II Development Board
NIosII软处理器快速入门
