Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics. - ppt download
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A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
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Figure 3 from Area-I/O flip-chip routing for chip-package co-design | Semantic Scholar
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Figure 4 from Area-I/O flip-chip routing for chip-package co-design | Semantic Scholar
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PPT - Area-I/O Flip-Chip Routing for Chip-Package Co-Design PowerPoint Presentation - ID:2266087
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